DFT Engineer
Job Description
DFT Engineer Jobs in Bangalore & Noida – ASIC / SoC Design for Test
Job overview
TalentCorner HR Services is hiring a Design for Test (DFT) Engineer for ASIC and SoC programmes, with the description naming Bangalore and Noida as work locations. The role asks for 5 to 8 years of experience in DFT, ASIC or SoC design and pays ₹50,000–₹2,00,000 per month. Candidates with an immediate to 60-day notice period are preferred.
You will define and implement the DFT architecture for complex designs and carry it through scan insertion, ATPG, memory and logic built-in self-test, and JTAG, then support silicon bring-up and production test. It is a core role in semiconductor design and sits between RTL, verification, physical design and test teams.
Key responsibilities
- Define and implement DFT architecture for complex ASIC/SoC designs
- Perform scan insertion, stitching and DFT logic integration
- Generate and validate ATPG patterns for high fault coverage
- Implement and verify MBIST, LBIST and JTAG (IEEE 1149.1/1149.6)
- Analyse test coverage and improve DFT quality metrics
- Debug DFT issues across simulation, synthesis and silicon bring-up
- Work with RTL, verification, physical design and test teams
- Make sure DFT work meets quality, timing and power requirements
- Support post-silicon validation and production testing
Skills required
Must have
- 5 to 8 years in DFT, ASIC or SoC design
- Knowledge of scan architecture, scan insertion and compression, ATPG, MBIST/LBIST and boundary scan
- Hands-on experience with tools such as Siemens Tessent, Synopsys DFT Compiler, Synopsys TestMAX or Cadence Modus
- Strong digital design fundamentals and Verilog/SystemVerilog
- Scripting in Tcl, Perl, Python or Shell, with Linux/Unix familiarity
- Understanding of STA and synthesis flows
Preferred
- Experience at advanced nodes such as 16nm, 7nm or 5nm and below
- Low-power methodology knowledge (UPF/CPF)
- SoC integration and physical design flow knowledge
- Production test and silicon bring-up experience
- CI/CD and automation scripting
Education
Bachelor’s or Master’s in Electronics, Electrical Engineering, VLSI, Computer Engineering or a related field.
DFT engineer jobs in Bangalore and Noida
Bangalore is India’s largest VLSI and semiconductor design cluster, and Noida is a major electronics and chip-design hub in the NCR. DFT engineers are in constant demand in both cities because every advanced chip needs a testability strategy, and experience with scan, ATPG and memory test on modern nodes is hard to find. Engineers with recent silicon bring-up experience are especially valued.
Frequently asked questions
How many years of experience are needed for the DFT Engineer role?
The description asks for 5 to 8 years of DFT, ASIC or SoC experience.
Which DFT tools should I know?
Siemens Tessent, Synopsys DFT Compiler, Synopsys TestMAX or Cadence Modus.
What notice period is preferred?
Immediate to 60 days.
How to apply
Log in as a candidate on iTroSys and apply through the DFT Engineer listing. The listing also asks for resumes to be emailed, so check the contact details on the page.
